1. Technical Field
The invention herein described relates to the processing of semiconductor wafers, for example during the fabrication of integrated circuits. More particularly, the invention relates to improving temperature uniformity across the wafer surface when processing semiconductor wafers.
2. Description of the Prior Art
A critical factor in assuring the high level of process reproducibility that is necessary for the efficient manufacture of semiconductor devices is the consistency or uniformity of processing conditions, such as temperature, pressure, etc. Process deviations, such as temperature gradients across a semiconductor wafer surface, especially in temperature sensitive processes, can seriously degrade process yields and therefore degrade the efficiency of the manufacturing process.
In the following discussion, the effect of lack of temperature uniformity across a wafer surface is examined in connection with a hot aluminum planarization process for purposes of example. This process is particularly useful where submicron device features are desired.
In submicron processes it is difficult to obtain sufficient step coverage for contact holes during device fabrication using conventional sputtering technology. In such processes, it is preferable to use hot aluminum planarization when forming both the contact plugs and the interconnection. This promising technology provides the advantages of avoiding the high complexity, high cost, high contact resistivity and poor controllability of the contact resistance, and the generation of contaminating particles associated a Tungsten CVD plug process. See, for example M. Taguchi, K. Koyama, Y. Sugano, Quarter Micron Hole filling With SiN Side Walls By Aluminum High Temperature Sputtering, IEEE VMIC Conference, pg. 219 (1992); H. H. Hoang, F. S. Chen, M. Zamanian, G.A. Dixit, C. C. Wei, F. T. Lious, Reliability Study of Planarized Aluminum Metallization, IEEE VMIC Conference, pg. 411 (1991); C. S. Park, S. I. Lee, J. H. Park, J. H. Sohn, D. Chin, J. G. Lee, AI-PLAPH Process For Planarized Double Metal CMOS Application, IEEE VMIC Conference, pg. 326 (1991); H. Nishimura, T. Yamada, S. Ogawa, Reliable Submicron Vias Using Aluminum Alloy High Temperature Sputter Filling, IEEE VMIC Conference, pg. 170 (1991); and H. Ono, Y. Ushiku, T. Yoda, Development of a Planarized AI-Si Contact Filling Technology, IEEE VMIC Conference, pg. 76 (1991).
In general, the hot aluminum planarization process can be classified as one of a high temperature reflow process, a cold/hot deposition process, or a coherent cold/hot deposition process. For example, in the high temperature reflow process, the wafer is heated to a temperature that is higher than about two-thirds of the melting point of aluminum (350.degree. C.), such that solid phase diffusion becomes dominant. The chemical potential difference induced by surface morphology drives the aluminum into the contact holes.
Various techniques are known for heating a wafer during processing. See, for example Muka, Heater Assembly For Thermal Processing of a Semiconductor Wafer in a Vacuum Chamber, U.S. Pat. No. 4,481,406, 6 Nov. 1984 (heater assembly including shields to reflect heat to a workpiece and thereby reduce process energy requirements); R. Anderson, T. Deacon, D. Carlson, Apparatus and Method For Substrate Heating Utilizing Various Infrared Means To Achieve Uniform Intensity, U.S. Pat. No. 5,179,677, 12 Jan. 1993 (reflector array within a remote heat source for balancing thermal radiation intensity across a heated surface); J. Wortman, F. Sorrell, J. Hauser, M. Fordham, Conical Rapid Thermal Processing Apparatus, U.S. Pat. No. 5,253,324, 12 Oct. 1993 (conical reflector for heating array); and K. Yamabe, K. Okumura, Method of Thermally Processing Semiconductor Wafers and an Apparatus Therefor, U.S. Pat. No. 5,259,883, 9 Nov. 1993 (thermal processing tube including a first, high temperature portion having a heat source, and a second, low temperature portion having a heat reflector).
Hot aluminum planarization technology has advantages over other techniques in terms of process simplicity and low resistivity, as well as the capability to fill-in contact holes with aspect ratio high than three. However, the process is sensitive to temperature non-uniformity across the surface of semiconductor wafers during flow processing of aluminum. Such temperature non-uniformity results in poor planarization of the aluminum film. A lack of temperature uniformity across the wafer surface also causes voiding of contact holes in a region that is about 20 mm from the edge of the wafer. The magnitude of this problem becomes apparent when one considers that modern semiconductor devices contain millions of transistors and, therefore, a typical wafer may contain more than a billion contacts. Failure to complete one contact can ruin a device.
This problem is especially pronounced when the processing temperature is higher than 500.degree. C. For example, for hot aluminum planarization, typical process parameters dictate that temperature variation across the wafer surface must be less than .+-.5.degree. C. at 600.degree. C.
Such temperature non-uniformity across the wafer surface is thought to be caused by heat loss or by a heating gas leak at the wafer edge. The heat loss mechanism is a radiative loss, since heat convection and conduction are negligible in a ultra-high vacuum ("UHV") system, such as a flow chamber, as is typically used for hot aluminum planarization and other processes.
Although it is known to heat a wafer during processing by applying heat in a uniform manner, it is not known how to assure temperature uniformity across a wafer surface, especially at the wafer edges. Lack of temperature uniformity across the wafer surface reduces device yield per wafer and thus makes the production of semiconductor devices significantly more expensive. A technique that provides improved temperature uniformity across the wafer surface would benefit the semiconductor industry, especially with regard to the new and emerging processing techniques, such as hot aluminum planarization, that are being developed to manufacture devices having submicron feature sizes.